Quest 01 / 11
Oct 2011 โ Dec 2014
๐งโ๐
๐ฆ Final-Exam Stego
โ Cleared
Assumption University of Thailand
Teaching Assistant โ Digital Logic Design (Verilog)
Three years TA-ing Digital Logic Design โ guiding labs, grading, and running tutorial classes for midterms and finals.
- Lab guidance for Verilog assignments
- Assisted grading and quizzes
- Ran tutorial classes for midterm & final exams